1. Field
Embodiments of the present invention generally relate to techniques for designing and manufacturing integrated circuits (ICs). More specifically, embodiments of the present invention relate to a technique for RLC modeling and extraction for three-dimensional integrated circuit (3D-IC) designs.
2. Related Art
Dramatic improvements in circuit design and manufacturing technology have made it possible to integrate hundreds of millions of transistors onto a single integrated circuit (IC) chip. More specifically, these improvements in IC integration densities have been achieved by shrinking IC feature sizes horizontally according to Moore's law. Because the scaling is performed horizontally, the IC chips are two-dimensional (2D) in nature (referred to as “2D-ICs”) and are coupled to other 2D-IC chips or packages through I/O pins.
As process scaling approaches the nanometer regime, improving performance through such horizontal scaling is becoming increasingly difficult because the IC feature sizes are approaching physical limits which results in large power consumption, manufacturing complexity, etc. Hence, the semiconductor industry is considering new technologies to continue to increase the integration densities.
Three-dimensional (3D)-IC technology is one such emerging technology that enables chip size reductions in the vertical direction by vertically stacking multiple IC dies. Two types of 3D-IC techniques have been proposed: package-level integration and wafer-level integration. Package-level integration techniques often suffer from limitations such as reduced interconnect density. On the other hand, wafer-level integration techniques, which use through-silicon vias (TSVs) or silicon interposers, can enable vertical IC-die integration and scaling without using external packaging connections. Such 3D-ICs are often vertically integrated through thinned silicon substrates and TSVs, and often require bonding techniques between vertically stacked dies.
Unfortunately, conventional electronic design automation (EDA) tools have been designed to work with 2D-ICs. As a result, conventional EDA tools usually cannot be used with 3D-ICs.
Hence, there is a need for EDA tools that can be used for designing 3D-ICs.